Kamal Kishor Jha

Assistant Professor

Academic Qualifications

  • Ph.D. VLSI Design, ABV-Indian Institute of Information Technology and Management (IAITM), Gwalior (2015).
  • M. Tech. VLSI Design, ABV-Indian Institute of Information Technology and Management (IAITM), Gwalior (2010).
  • B. E. Electronics and Communication Engineering, RGTU Bhopal (2008).

Research interests

  • Novel Semiconductor Device Design and Modeling.
  • Device-Circuit Co-Design.
  • Hybrid Device-Circuit Interaction.
  • Analog and Mixed Signal Design.
  • Tunnel FET, Graphene FET and other related devices.
  • Low power VLSI Design.

Work Experience

  • Assistant Professor at Manav Rachna International University (MRIU), Faridabad (2010-2011).
  • Faculty Associate at Indian Institute of Information Technology, Kanpur, Uttar Pradesh (June 2015- October 2015).
  • Assistant Professor at Indian Institute of Information Technology, Kanpur, Uttar Pradesh (November 2015 Onwards)
  • Visiting Faculty at CIIT Kanpur Nagar.

Publications

International Peer Review Journals
  • Kamal K. Jha, Varun Sharma, and Manisha Pattanaik, Line Tunnel FET Parameter Variations:A Simulation Study, Journal of Computational and Theoretical Nanoscience, Vol. 12, No. 09, pp. 1-4, 2015.
  • Kamal K. Jha, Varun Sharma, and Manisha Pattanaik, Impact of Temperature Variations on Line Tunnel FET for Low Power Applications, Journal of Computational and Theoretical Nanoscience, Vol. 12, No. 11, pp. 1-4, 2015.
  • Kamal K. Jha and Manisha pattanaik, Enhanced ON Current Pocket Tunnel FET for Circuits Operating Near-Threshold, Quantum matter, Vol. 4, No. 2, pp. 1-4, 2015.
  • Abhishek Mishra, Kamal K. Jha, Manisha Pattanaik, Parameter Variation Aware Hybrid TFET-CMOS Based Power Gating Technique with a Temperature Variation Tolerant Sleep Mode, Microelectronics Journal, Vol. 45, No. 11, pp. 1515-1521, 2014.
  • Kamal K. Jha, Manisha pattanaik, Analysis of Pocket Double Gate Tunnel FET for Low Standby Power Logic Circuits, International Journal of VLSI Design & Communication Systems (VLSICS), Vol. 4, No. 6, pp. 27-34, 2022.
  • Kamal Kishor Jha, Anurag Srivastava, Dual Material Single Layer (DMSL) Segmentation of Insulator with High-k/Metal for Leakage Reduction and Low Power Application, ISST Journal of Electrical & Electronics Engineering Vol. 1 No.1, pp. 17-21, 2010.
International Conferences
  • Jagdeep Rahul, Anurag Srivastava, Shekhar Yadav, Kamal Kishor Jha, Performance Evaluation of Junctionless Vertical Double Gate MOSFET, International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, March 2012.
  • Shekhar Yadav, Anurag Srivastava, Jagdeep Rahul, Kamal Kishor Jha, TCAD Assessment of Nonconventional Dual Insulator Double Gate MOSFET, International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, March 2012.
  • Kamal Kishor Jha, Anurag Srivastava, Manisha Pattanaik, Pradip Swarnkar, Design and Estimation of Drive Current of Scaled Devices by Selection of Suitable Metal Gate with Zr Oxide Dielectric in nm Regime, Proceedings of the International Conference on Nanoscience, Engineering and Technology (ICONSET), November 2011.
  • Kamal Kishor Jha, Ankita Jain, Manisha Pattanaik, Anurag Srivastava, Performance Analysis of NMOS for Higher Speed and Low Power Applications, DATICS-Future Tech-10, IEEE Conference, South Korea,2010.
  • Kamal Kishor Jha, Anurag Srivastava, DQWRTD MOSFET for Leakage Reduction and Low Power Applications, DATICS-Future Tech-10, IEEE Conference, South Korea, 2010.
National Conferences
  • Kamal Kishor Jha, Anurag Srivastava, Gate Leakage Reduction through high-k/metal gate, National Seminar on Advances in Materials and Devices, ITM University, Gurgaon, India, May 2010.
  • Kamal Kishor Jha, Anurag Srivastava, Scaling of NMOS 600-90nm, Seminar on Advancement & Future Trends in VLSI Design & Embedded Systems-ATVES, Feb. 2010.

Courses of interest

  • Analog Electronics and Circuits.
  • Electronic Devices and Circuits.
  • Digital Electronics.
  • Analog CMOS Integrated Circuits Design.
  • Digital CMOS Integrated Circuits Design.
  • Nano-scale Device Modeling.
  • Nano-electronics/Nanotechnology.

Membership

  • Member, IEEE

Contact

Email: kamal@akashic.ac.in, kamaliAITm@gmail.com
Phone::+91-7624024051